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cy8c20x37/37s/47/47s/67/67s 1.8 v capsense ? controller with smartsense? auto-tuning ? 31 buttons, 6 sliders cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-69257 rev. *f revised july 3, 2012 1.8 v capsense ? controller with smartsense? auto-tuning support features quietzone? controller ? patented capacitive sigma delta plus (csd plus?) sensing algorithm for robust performance ? high sensitivity (0.1 pf) and best-in-class snr performance to support: ? ideal for proximity solutions ? overlay thickness of 15 mm for glass and 5 mm plastic ? superior noise immunity performance against conducted and radiated noise and ultra low radiated emissions ? reliable and robust touch performance in noisy environ- ments ? standardized user modules for overcoming noise low power capsense ? block with smartsense? auto-tuning ? supports a combination of up to 31 buttons or 6 sliders, prox- imity sensors ? low average power consumption - 28 ? a for each sensor at runtime (wake from sleep and scan sensors every 125 ms) ? smartsense auto-tuning ? sets and maintains optimal sensor performance during runtime ? eliminates system tuning dur ing development and produc- tion ? compensates for variations in manufacturing process driven shield available on five gpio pins ? max load of 100 pf at 3 mhz ? frequency range: 375 khz to 3 mhz ? delivers best-in class water tolerant designs ? robust proximity sensing in the presence of metal objects powerful harvard-architecture processor ? m8c cpu with a maximum speed of 24 mhz ? operating range: 1.71 v to 5.5 v ? standby mode: 1.1 a (typ) ? deep sleep: 0.1 a (typ) ? temperature range: ?40 c to +85 c flexible on-chip memory ? 8 kb flash, 1 kb sram ? 16 kb flash, 2 kb sram ? 32 kb flash, 2 kb sram ? 50,000 flash erase/write cycles ? in-system programming capability four clock sources ? internal main oscillato r (imo): 6/12/24 mhz ? internal low-speed oscillator (ilo) at 32 khz for watchdog and sleep timers ? rc crystal oscillator ? clock input programmable pin configurations ? up to 32 general-purpose i/os (gpios) ? dual mode gpio ? high sink current of 25 ma for each gpio. total 120 ma maximum sink current per chip ? 5 ma source current on port 0 and 1 and 1 ma on port 2,3 and 4 ? configurable internal pull-up, high-z, and open drain modes ? selectable, regulated digital i/o on port 1 ? configurable input threshold on port 1 versatile analog mux ? common internal analog bus ? simultaneous connection of i/o ? high power supply rejection ratio (psrr) comparator ? low-dropout voltage regulator for all analog resources additional system resources ? i 2 c slave: ? selectable to 50 khz, 100 khz, or 400 khz ? selectable clock stretch or forced nack mode ? implementation during sleep modes with less than 100 a ?i 2 c wake from sleep with hardware address validation ? 12 mhz spi master and slave ? three 16-bit timers ? watchdog and sleep timers ? internal voltage reference ? integrated supervisory circuit ? 10-bit incremental analog-to-digital converter (adc) ? two general-purpose high speed, low power analog compar- ators complete development tools ? free development tool (psoc designer?) package options ? 16-pin soic (150 mil) ? 16-pin qfn ? 3 3 0.6 mm ? 24-pin qfn ? 4 4 0.6 mm ? 32-pin qfn ? 5 5 0.6 mm ? 48-pin qfn ? 6 6 0.6 mm ? 30-ball wlcsp [1] note 1. contact your nearest cypress sales office for details.
cy8c20x37/37s/47/47s/67/67s document number: 001-69257 rev. *f page 2 of 39 logic block diagram capsense system 1k/2 k sram interrupt controller sleep and watchdog multiple clock sources internal low speed oscillator ( ilo) 6/12/ 24 mhz internal ma in oscillator (imo) psoc core cpu core (m8c) supervisory rom (srom) 8k/16k/32 k flash nonvolatile memory system resources system bus analog reference system bus port 3 port 2 port 1 port 0 capsense module global analog interconnect 1.8/2.5/3 v ldo analog mux i2c slave spi master/ slave por and lvd system resets internal voltage references three 16- bit programmable timers pwrsys (regulator) port 4 digital clocks comparator #2 comparator #1 [2] note 2. internal voltage regulator for internal circuitry
cy8c20x37/37s/47/47s/67/67s document number: 001-69257 rev. *f page 3 of 39 contents psoc ? functional overview ............................................ 4 psoc core .................................................................. 4 capsense system ....................................................... 4 additional system resources ..................................... 5 getting started .................................................................. 5 application notes/design guid es ................................ 5 development kits ........................................................ 5 training ....................................................................... 5 cypros consultants .................................................... 5 solutions library .......................................................... 5 technical support ....................................................... 5 designing with psoc designer ....................................... 6 select components ..................................................... 6 configure components .......... .............. .............. ......... 6 organize and connect .............. .............. ........... ......... 6 generate, verify, and debug ....................................... 6 pinouts .............................................................................. 7 16-pin soic (12 sensing inpu ts) ................................ 7 16-pin qfn (12 sensing inputs) .................................. 8 24-pin qfn (20 sensing inputs) .................................. 9 30-ball wlcsp (26 sensing inputs) .......................... 10 32-pin qfn (26 sensing inputs) ................................ 11 48-pin qfn (33 sensing inputs) ................................ 12 electrical specifications ................................................ 13 absolute maximum ratings .... ................................... 13 operating temperature ............................................. 13 dc chip-level specifications .................................... 14 dc gpio specifications ............................................ 15 dc analog mux bus specifications ........................... 17 dc low power comparator sp ecifications ............... 17 comparator user module electr ical specifications ... 18 adc electrical specifications .................................... 18 dc por and lvd specifications .............................. 19 dc programming specifications ............................... 19 dc i2c specifications ............................................... 20 shield driver dc specificati ons ................................ 20 dc idac specifications ............................................ 20 ac chip-level specifications .................................... 21 ac general purpose i/o specifications .................... 22 ac comparator specifications .................................. 22 ac external clock specifications .............................. 22 ac programming specifications ................................ 23 ac i2c specifications ................................................ 24 packaging information ................................................... 27 thermal impedances ................................................. 30 capacitance on crystal pins .. ............. .............. ........ 30 solder reflow peak temperat ure ............................. 30 development tool selection .. .............. .............. ........... 31 software .................................................................... 31 development kits ...................................................... 31 evaluation tools ........................................................ 31 device programmers ............. .................................... 31 accessories (emulation and programming) .............. 32 third party tools ....................................................... 32 build a psoc emulator into yo ur board .................... 32 ordering information ...................................................... 33 ordering code definitions ..... .................................... 34 acronyms ........................................................................ 35 reference documents .................................................... 35 document conventions ......... .................................... 35 units of measure ....................................................... 35 numeric naming .................... .................................... 36 glossary .......................................................................... 36 document history page ................................................. 37 sales, solutions, and legal information ...................... 39 worldwide sales and design s upport ......... .............. 39 products .................................................................... 39 psoc solutions ......................................................... 39
cy8c20x37/37s/47/47s/67/67s document number: 001-69257 rev. *f page 4 of 39 psoc ? functional overview the psoc family consists of many devices with on-chip controllers. these devices are designed to replace multiple traditional mcu-based system components with one low-cost single-chip programmable component. a psoc device includes configurable blocks of analog and digital logic, and programmable interconnect. this architecture makes it possible for you to create customized peri pheral configurations, to match the requirements of each individua l application. additionally, a fast central processing unit (cpu), flash program memory, sram data memory, and configurable i/o are included in a range of convenient pinouts. the architecture for this device family, as shown in the logic block diagram on page 2 , consists of three main areas: the core capsense analog system system resources a common, versatile bus allows connection between i/o and the analog system. each cy8c20x37/47/67/s psoc device includes a dedicated capsense block that provides sensing and scanning control circuitry for capacitive sensing applications. depending on the psoc package, up to 34 gpios are also included. the gpios provide access to the mcu and analog mux. psoc core the psoc core is a powerful engine that supports a rich instruction set. it encompasses sram for data storage, an interrupt controller, sleep and watchdog timers, and imo and ilo. the cpu core, called the m8c, is a powerful processor with speeds up to 24 mhz. the m8c is a 4-million instructions per second (mips), 8-bit harvard-architecture microprocessor. capsense system the analog system contains the capacitive sensing hardware. several hardware algorithms are supported. this hardware performs capacitive sensing and scanning without requiring external components. the analog system is composed of the capsense psoc block and an internal 1 v or 1.2 v analog reference, which together support capacitive sensing of up to 31 inputs [3] . capacitive sensing is configurable on each gpio pin. scanning of enabled capsense pins is completed quickly and easily across multiple ports. smartsense ? auto-tuning smartsense auto-tuning is an in novative solution from cypress that removes manual tuning of capsense applications. this solution is easy to use and provides robust noise immunity. it is the only auto-tuning solution that establishes, monitors, and maintains all required tuning parameters of each sensor during run time. smartsense auto-tuning allows engineers to go from prototyping to mass production without retuning for manufacturing variations in pcb and/or overlay material properties. figure 1. capsense system block diagram analog multiplexer system the analog mux bus can connect to every gpio pin. pins are connected to the bus individually or in any combination. the bus also connects to the analog system for analysis with the capsense block comparator. switch-control logic enables selected pins to precharge continuously under hardware control. this enables capacitive measurement for applications su ch as touch sensing. other multiplexer applications include: complex capacitive sensing in terfaces, such as sliders and touchpads. chip-wide mux that allows analog input from any i/o pin. crosspoint connection between any i/o pin combinations. idac reference buffer vr analog global bus cap sense counters comparator mux mux refs capsense clock select oscillator csclk imo cs1 cs2 csn cexternal (p0[1] or p0[3]) note 3. 34 gpios = 31 pins for capacitive sensing+2 pins for i 2 c + 1 pin for modulator capacitor.
cy8c20x37/37s/47/47s/67/67s document number: 001-69257 rev. *f page 5 of 39 additional system resources system resources provide additional capability, such as configurable i 2 c slave, spi master /slave communication interface, three 16-bit progr ammable timers, various system resets supported by the m8c low voltage detection and power- on reset. the merits of each system resource are listed here: the i 2 c slave/spi master-slave module provides 50/100/ 400 khz communication over two wires. spi communication over three or four wires runs at speeds of 46.9 khz to 3 mhz (lower for a slower system clock). the i 2 c hardware address recognition feature reduces the already low power consumption by eliminating the need for cpu intervention until a packet addressed to the target device is received. the i 2 c enhanced slave interface appears as a 32-byte ram buffer to the external i 2 c master. using a simple predefined protocol, the master controls the read and write pointers into the ram. when this method is e nabled, the slave does not stall the bus when receiving data bytes in active mode. for usage details, see the application note i2c enhanced slave operation - an56007 . low-voltage detection (lvd) interrupts can signal the application of falling voltage levels, while the advanced power- on reset (por) circuit eliminates the need for a system supervisor. an internal reference provides an absolute reference for capacitive sensing. a register-controlled bypass mode allows the user to disable the ldo regulator. getting started the quickest way to understand psoc silicon is to read this datasheet and then use the psoc designer integrated development environment (ide). this datasheet is an overview of the psoc integrated circuit and presents specific pin, register, and electrical specifications. for in depth information, along with detailed programming details, see the technical reference manual for the cy8c20x37/ 47/67/s psoc devices. for up-to-date ordering, packaging, and electrical specification information, see the latest psoc device datasheets on the web at www.cypress.com/psoc . application notes/design guides application notes and design guides are an excellent introduction to the wide variety of possible psoc designs. they are located at www.cypress.com/gocapsense . select application notes under the related documentation tab. development kits psoc development kits are available online from cypress at www.cypress.com/shop and through a growing number of regional and global distributors, which include arrow, avnet, digi- key, farnell, future electronics, and newark. see development kits on page 31 . training free psoc and capsense technical training (on demand, webinars, and workshops) is available online at www.cypress.com/training . the training covers a wide variety of topics and skill levels to assist you in your designs. cypros consultants certified psoc consultants offer everything from technical assistance to completed psoc designs. to contact or become a psoc consultant go to www.cypress.com/cypros . solutions library visit our growing library of solution focused designs at www.cypress.com/solutions . here you can find various application designs that include firmware and hardware design files that enable yo u to complete your designs quickly. technical support for assistance with technical issues, search knowledgebase articles and forums at www.cypress.com/support . if you cannot find an answer to your question, create a technical support case or call technical support at 1-800-541-4736.
cy8c20x37/37s/47/47s/67/67s document number: 001-69257 rev. *f page 6 of 39 designing with psoc designer the psoc development process can be summarized in the following four steps: 1. select user modules 2. configure user modules 3. organize and connect 4. generate and verify select components psoc designer provides a library of pre-built, pre-tested hardware peripheral components called ?user modules?. user modules make selecting and implementing peripheral devices, both analog and digital, simple. configure components each of the user modules you select establishes the basic register settings that implement the selected function. they also provide parameters and properties that allow you to tailor their precise configuration to your pa rticular application. the user module parameters permit you to establish the pulse width and duty cycle. configure the pa rameters and properties to correspond to your chosen application. enter values directly or by selecting values from drop-d own menus. all the user modules are documented in datasheets that may be viewed directly in psoc designer or on the cypress website. these user module datasheets explain the internal operation of the user module and provide performance specifications. each datasheet describes the use of each user module parameter, and other information you may need to successfully implement your design. organize and connect you build signal chains at the chip level by interconnecting user modules to each other and the i/o pins. you perform the selection, configuration, and ro uting so that you have complete control over all on-chip resources. generate, verify, and debug when you are ready to test the hardware configuration or move on to developing code for the project, you perform the ?generate configuration files? step. this causes psoc designer to generate source code that automat ically configures the device to your specification and provides the software for the system. the generated code provides application programming interfaces (apis) with high-level functi ons to control and respond to hardware events at run time and interrupt service routines that you can adapt as needed. a complete code development environment allows you to develop and customize your applications in c, assembly language, or both.
cy8c20x37/37s/47/47s/67/67s document number: 001-69257 rev. *f page 7 of 39 pinouts the cy8c20x37/47/67/s psoc device is available in a variety of packages, which are listed and illustrated in the following tabl es. every port pin (labeled with a ?p?) is capable of digital i/o and connection to the common analog bus. however, v ss , v dd , and xres are not capable of digital i/o. 16-pin soic (12 sensing inputs) table 1. pin definitions ? cy 8c20237-24sxi, cy8c20247-24sxi pin no. type name description figure 2. cy8c20237-24sxi, cy8c20247-24sxi device digital analog 1 i/o i p0[3] integrating input 2 i/o i p0[1] integrating input 3 i/o i p2[5] 4 i/o i p2[3] 5 i/o i p1[7] 6 i/o i p1[5] 7 i/o i p1[3] 8 i/o i p1[1] issp clk [4] , i 2 c scl, spi mosi 9 power v ss ground connection 10 i/o i p1[0] issp data [4] , i 2 c sda, spi clk [5] 11 i/o i p1[2] driven shield output (optional) 12 i/o i p1[4] optional external clock (extclk) 13 input xres active high external reset with internal pull-down 14 i/o i p0[4] 15 power v dd supply voltage 16 i/o i p0[7] legend a = analog, i = input, o = output, oh = 5 ma high output drive, r = regulated output. soic p0[7], ai v dd p0[4], ai xres p1[4], extclk p1[2], ai p1[0], issp data, i 2 c sda, spi clk, ai v ss 16 15 14 13 12 11 1 2 3 4 5 6 7 8 ai, p0[3] ai, p0[1] ai, p2[5] ai, p2[3] ai, p1[7] ai, p1[5] ai, p1[3] ai, issp clk, i 2 c scl, spi mosi, p1[1] 10 9 notes 4. on power-up, the sda(p1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep c lock cycles. the scl(p1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. on reset, after xres de-asserts, the sda and the scl lines drive resistive low for 8 sleep clock cycles and transition to high im pedance state. hence, during power-up or reset event, p1[1] and p1[0] may disturb the i2c bus. use alternate pins if you encounter issues. 5. alternate spi clock.
cy8c20x37/37s/47/47s/67/67s document number: 001-69257 rev. *f page 8 of 39 16-pin qfn (12 sensing inputs) table 2. pin definition s ? cy8c20237, cy8c20247/s [6] pin no. type name description figure 3. cy8c20237, cy8c20247/s device digital analog 1 i/o i p2[5] crystal output (xout) 2 i/o i p2[3] crystal input (xin) 3 iohr i p1[7] i 2 c scl, spi ss 4 iohr i p1[5] i 2 c sda, spi miso 5 iohr i p1[3] spi clk 6 iohr i p1[1] issp clk [7] , i 2 c scl, spi mosi 7 power v ss ground connection 8 iohr i p1[0] issp data [7] , i 2 c sda, spi clk [8] 9 iohr i p1[2] driven shield output (optional) 10 iohr i p1[4] optional external clock (extclk) 11 input xres active high external reset with internal pull-down 12 ioh i p0[4] 13 power v dd supply voltage 14 ioh i p0[7] 15 ioh i p0[3] integrating input 16 ioh i p0[1] integrating input legend a = analog, i = input, o = output, oh = 5 ma high output drive, r = regulated output. qfn (top view) ai , xout, p2[5] ai , i2 c scl, spi ss, p1[7] ai , i2 c sda, spi miso, p1[5] ai, spi cl k , p1[3] 1 2 3 4 11 10 9 16 15 14 13 p0[3], ai p0[7], ai v dd p0[4] , ai ai, issp clk, spi mosi, p1[1] ai, issp data , i2c sda, spi cl k , p1[0] p1[2] , ai ai , xin, p2[3] p1[4] , extclk, ai xres p0[1], ai v ss 12 5 6 7 8 notes 6. no center pad. 7. on power-up, the sda(p1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep c lock cycles. the scl(p1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. on reset, after xres de-asserts, the sda and the scl lines drive resistive low for 8 sleep clock cycles and transition to high im pedance state. hence, during power-up or reset event, p1[1] and p1[0] may disturb the i 2 c bus. use alternate pins if you encounter issues. 8. alternate spi clock.
cy8c20x37/37s/47/47s/67/67s document number: 001-69257 rev. *f page 9 of 39 24-pin qfn (20 sensing inputs) table 3. pin definition s ? cy8c20337, cy8c20347/s [9] pin no. type name description figure 4. cy8c20337, cy8c20347/s device digital analog 1 i/o i p2[5] crystal output (xout) 2 i/o i p2[3] crystal input (xin) 3 i/o i p2[1] 4 iohr i p1[7] i 2 c scl, spi ss 5 iohr i p1[5] i 2 c sda, spi miso 6 iohr i p1[3] spi clk 7 iohr i p1[1] issp clk [10] , i 2 c scl, spi mosi 8 nc no connection 9 power v ss ground connection 10 iohr i p1[0] issp data [10] , i 2 c sda, spi clk [11] 11 iohr i p1[2] driven shield output (optional) 12 iohr i p1[4] optional external clock input (extclk) 13 iohr i p1[6] 14 input xres active high external reset with internal pull-down 15 i/o i p2[2] driven shield output (optional) 16 i/o i p2[4] driven shield output (optional) 17 ioh i p0[0] driven shield output (optional) 18 ioh i p0[2] 19 ioh i p0[4] 20 power v dd supply voltage 21 ioh i p0[7] 22 ioh i p0[3] integrating input 23 power v ss ground connection 24 ioh i p0[1] integrating input cp power v ss center pad must be connected to ground legend a = analog, i = input, o = output, oh = 5 ma high output drive, r = regulated output. ai, issp data 2 , i2c sda, spi clk, p1[0] qfn (top view) ai, i2c scl, spi ss, p1[7] ai, i2c sda, spi miso, p1[5] ai, spi clk, p1[3] 1 2 3 4 5 6 18 17 16 15 14 13 p0[0], ai p2[4], ai 24 23 22 21 20 19 v ss p0[3], ai p0[7], ai v dd p0[2], ai 7 8 9 10 11 12 spi mosi, p1[1] ai, p1[2] ai, p2[1] nc p1[6], ai ai, extclk, p1[4] xres p2[2], ai p0[4], ai ai, issp clk 2 , i2c scl p0[1], ai v ss ai, xout, p2[5] ai, xin, p2[3] notes 9. the center pad (cp) on the qfn package must be connected to ground (v ss ) for best mechanical, thermal, and electrical performance. if not connected to ground, it must be electrically floated an d not connected to any other signal. 10. on power-up, the sda(p1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. the scl(p1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. on reset, after xres de-asserts, the sda and the scl lines drive resistive low for 8 sleep clock cycles and transition to high im pedance state. hence, during power-up or reset event, p1[1] and p1[0] may disturb the i 2 c bus. use alternate pins if you encounter issues. 11. alternate spi clock.
cy8c20x37/37s/47/47s/67/67s document number: 001-69257 rev. *f page 10 of 39 30-ball wlcsp (26 sensing inputs) table 4. pin definitions ? cy8c20767, cy8c20747 30-ball part pinout (wlcsp) pin no. type name description digital analog figure 5. cy8c20767, cy8c20747 30-ball wlcsp a1 ioh i p0[2] bottom view top view a2 ioh i p0[6] a3 power v dd supply voltage a4 ioh i p0[1] integrating input a5 i/o i p2[7] b1 i/o i p4[2] b2 ioh i p0[0] driven shield output (optional) b3 ioh i p0[4] b4 ioh i p0[3] integrating input b5 i/o i p2[5] crystal output (xout) c1 i/o i p2[2] driven shield output (optional) c2 i/o i p2[4] driven shield output (optional) c3 i/o i p0[7] c4 ioh i p3[2] c5 i/o i p2[3] crystal input (xin) d1 i/o i p2[0] driven shield output (optional) d2 i/o i p3[0] d3 i/o i p3[1] d4 i/o i p3[3] d5 i/o i p2[1] e1 input xres active high external reset with internal pull-down e2 iohr i p1[6] e3 iohr i p1[4] optional external clock input (ext clk) e4 iohr i p1[7] i 2 c scl, spi ss e5 iohr i p1[5] i 2 c sda, spi miso f1 iohr i p1[2] driven shie ld output (optional) f2 iohr i p1[0] issp data [12] , i 2 c sda, spi clk [13] f3 power v ss supply ground f4 iohr i p1[1] issp clk [12] , i 2 c scl, spi mosi f5 iohr i p1[3] spi clk legend: a = analog, i = input, o = output, oh = 5 ma high output drive, r = regulated output 54321 a b c d e f 12345 b c d e f a notes 12. on power-up, the sda(p1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. the scl(p1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. on reset, after xres de-asserts, the sda and the scl lines drive resistive low for 8 sleep clock cycles and transition to high im pedance state. hence, during power-up or reset event, p1[1] and p1[0] may disturb the i 2 c bus. use alternate pins if you encounter issues. 13. alternate spi clock.
cy8c20x37/37s/47/47s/67/67s document number: 001-69257 rev. *f page 11 of 39 32-pin qfn (26 sensing inputs) table 5. pin definitions ? cy8c 20437, cy8c20447/s, cy8c20467/s [14] pin no. type name description figure 6. cy8c20437, cy8c20447/s, cy8c20467/s device digital analog 1 ioh i p0[1] integrating input 2 i/o i p2[5] crystal output (xout) 3 i/o i p2[3] crystal input (xin) 4 i/o i p2[1] 5 i/o i p4[3] 6 i/o i p3[3] 7 i/o i p3[1] 8 iohr i p1[7] i 2 c scl, spi ss 9 iohr i p1[5] i 2 c sda, spi miso 10 iohr i p1[3] spi clk. 11 iohr i p1[1] issp clk [15] , i 2 c scl, spi mosi. 12 power v ss ground connection 13 iohr i p1[0] issp data [15] , i 2 c sda, spi clk [16] 14 iohr i p1[2] driven shield output (optional) 15 iohr i p1[4] optional external clock input (extclk) 16 iohr i p1[6] 17 input xres active high external reset with internal pull-down 18 i/o i p3[0] 19 i/o i p3[2] 20 i/o i p4[0] 21 i/o i p4[2] 22 i/o i p2[0] driven shield output (optional) 23 i/o i p2[2] driven shield output (optional) 24 i/o i p2[4] driven shield output (optional) 25 ioh i p0[0] driven shield output (optional) 26 ioh i p0[2] 27 ioh i p0[4] 28 ioh i p0[6] 29 power v dd 30 ioh i p0[7] 31 ioh i p0[3] integrating input 32 power v ss ground connection cp power v ss center pad must be connected to ground legend a = analog, i = input, o = output, oh = 5 ma high output drive, r = regulated output. ai , p0[1] ai , p2[5] ai , xout , p2[3] ai , xin , p2[1] ai , p4[3] ai , p3[3] qfn (top view) 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 vss p0 [3 ], ai p0 [6], ai v dd p0 [4 ], ai p0 [2 ], ai p0 [0 ], ai ai , p3[1] ai , i2 c scl, spi ss, p1[7] p2[4] , ai p2[2] , ai p3[0] , ai xres ai , i 2c sd a , sp i mi so , p 1[ 5] ai, spi clk, p1[3] vss ai , p 1[ 2] ai , e xt clk , p 1[ 4] ai , p 1[ 6] p2[0] , ai p4[2] , ai p4[0] , ai p3[2] , ai p0 [7 ], ai ai , issp clk , i2c scl, spi mosi, p1[1] ai , issp d ata , i 2c sda, spi clk, p1[ 0] notes 14. the center pad (cp) on the qfn package must be connected to ground (v ss ) for best mechanical, thermal, and electrical performance. if not connected to ground, it must be electrically floated an d not connected to any other signal. 15. on power-up, the sda(p1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. the scl(p1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. on reset, after xres de-asserts, the sda and the scl lines drive resistive low for 8 sleep clock cycles and transition to high im pedance state. hence, during power-up or reset event, p1[1] and p1[0] may disturb the i 2 c bus. use alternate pins if you encounter issues. 16. alternate spi clock.
cy8c20x37/37s/47/47s/67/67s document number: 001-69257 rev. *f page 12 of 39 48-pin qfn (33 sensing inputs) table 6. pin definitions ? cy 8c20637, cy8c20647/s, cy8c20667/s [17, 18] pin no. digital analog name description figure 7. cy8c20637, cy8c20647/s, cy8c20667/s device 1 nc no connection 2 i/o i p2[7] 3 i/o i p2[5] crystal output (xout) 4 i/o i p2[3] crystal input (xin) 5 i/o i p2[1] 6 i/o i p4[3] 7 i/o ip4[1] 8 i/o i p3[7] 9 i/o i p3[5] 10 i/o i p3[3] 11 i/o i p3[1] 12 iohr i p1[7] i 2 c scl, spi ss 13 iohr i p1[5] i 2 c sda, spi miso 14 nc no connection 15 nc no connection 16 iohr i p1[3] spi clk 17 iohr i p1[1] issp clk [17] , i 2 c scl, spi mosi 18 power v ss ground connection 19 nc no connection 20 nc no connection 21 power v dd supply voltage 22 iohr i p1[0] issp data [17] , i 2 c sda, spi clk [19] 23 iohr i p1[2] driven shield output (optional) 24 iohr i p1[4] optional external clock input (extclk) 25 iohr i p1[6] 26 input xres active high external reset with internal pull-down 27 i/o i p3[0] 28 i/o ip3[2] 29 i/o ip3[4] pin no. digital analog name description 30 i/o ip3[6] 40 ioh i p0[6] 31 i/o i p4[0] 41 power v dd supply voltage 32 i/o i p4[2] 42 nc no connection 33 i/o i p2[0] driven shield output (optional) 43 nc no connection 34 i/o i p2[2] driven shield output (optional) 44 ioh i p0[7] 35 i/o i p2[4] driven shield output (optional) 45 nc no connection 36 nc no connection 46 ioh i p0[3] integrating input 37 ioh i p0[0] driven shield output (optional) 47 power v ss ground connection 38 ioh i p0[2] 48 ioh i p0[1] integrating input 39 ioh i p0[4] cp power v ss center pad must be connected to ground legend a = analog, i = input, o = output, nc = no connection h = 5 ma high output drive, r = regulated output. qfn (top view) vss p0[3], ai nc , p0[7], ai vdd p0[6], ai p0[2], ai p0[0], ai 10 11 12 ai , p2[7] nc ai , xout, p2[5] ai , xin , p2[3] ai , p2[1] ai , p4[3] ai , p4[1] ai , p3[7] ai , p3[5] ai , p3[3] ai p 3[1] ai , i2 c scl, spi ss, p1[ 7] 35 34 33 32 31 30 29 28 27 26 25 36 48 47 4 6 45 44 43 42 41 4 0 39 38 37 p2[4], ai p2[2], ai p2[0], ai p4[2], ai p4[0], ai p3[6], ai p3[4], ai p3[2], ai p3[0 ], ai xres p1[6], ai nc 1 2 3 4 5 6 7 8 9 13 14 15 16 17 18 19 20 21 22 23 24 i2c sda, spi miso, a i, p1[5] nc spiclk,ai,p1[3] ai , issp cl k , i2c scl, spi mosi, p1[1] vss nc nc vdd ai, issp data 1 ,i2csda,spicl k ,p1[0] ai, p 1[ 2] ai, extclk, p1[4] nc nc nc p0[4], ai p0[1], ai notes 17. on power-up, the sda(p1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. the scl(p1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. on reset, after xres de-asserts, the sda and the scl lines drive resistive low for 8 sleep clock cycles and transition to high im pedance state. hence, during power-up or reset event, p1[1] and p1[0] may disturb the i 2 c bus. use alternate pins if you encounter issues. 18. the center pad (cp) on the qfn package must be connected to ground (v ss ) for best mechanical, thermal, and electrical performance. if not connected to ground, it must be electrically floated an d not connected to any other signal. 19. alternate spi clock.
cy8c20x37/37s/47/47s/67/67s document number: 001-69257 rev. *f page 13 of 39 electrical specifications this section presents the dc and ac electrical specifications of the cy8c20x37/47/67/s psoc devi ces. for the latest electrical specifications, confirm that you have the mo st recent datasheet by visiting the web at http://www.cypress.com/psoc . figure 8. voltage versus cpu frequency absolute maximum ratings exceeding maximum ratings may shorten the useful li fe of the device. user guidelines are not tested. operating temperature 5.5 v 750 khz 24 mhz cpu frequency v dd voltage 1. 71 v 3 mhz v a l i d o p e r a t i n g r e g i o n table 7. absolute maximum ratings symbol description conditions min typ max units t stg storage temperature higher storage temperatures reduce data retention time. recommended storage temperature is +25 c 25 c. extended duration storage temperatures above 85 c degrades reliability. ?55 +25 +125 c v dd supply voltage relative to v ss ? ?0.5 ? +6.0 v v io dc input voltage ? v ss ? 0.5 ? v dd + 0.5 v v ioz dc voltage applied to tristate ? v ss ? 0.5 ? v dd + 0.5 v i mio maximum current into any port pin ? ?25 ? +50 ma esd electro static discharge voltage human body model esd 2000 ? ? v lu latch up current in accordance with jesd78 standard ? ? 200 ma table 8. operating temperature symbol description conditions min typ max units t a ambient temperature ? ?40 ? +85 c t c commercial temperature range ? 0 70 c t j operational die temperature the temperature rise from ambient to junction is package specific. see the thermal imped- ances on page 30 . the user must limit the power consumption to comply with this requirement. ?40 ? +100 c
cy8c20x37/37s/47/47s/67/67s document number: 001-69257 rev. *f page 14 of 39 dc chip-level specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 9. dc chip-level specifications symbol description conditions min typ max units v dd [20, 21, 22] supply voltage see table dc por and lvd specifications on page 19 1.71 ? 5.50 v i dd24 supply current, imo = 24 mhz conditions are v dd ? 3.0 v, t a = 25 c, cpu = 24 mhz. capsense running at 12 mhz, no i/o sourcing current ? 2.88 4.00 ma i dd12 supply current, imo = 12 mhz conditions are v dd ? 3.0 v, t a = 25 c, cpu = 12 mhz. capsense running at 12 mhz, no i/o sourcing current ? 1.71 2.60 ma i dd6 supply current, imo = 6 mhz conditions are v dd ? 3.0 v, t a = 25 c, cpu = 6 mhz. capsense running at 6 mhz, no i/o sourcing current ? 1.16 1.80 ma i sb0 deep sleep current v dd ? 3.0 v, t a = 25 c, i/o regulator turned off ? 0.10 1.1 ? a i sb1 standby current with por, lvd and sleep timer v dd ? 3.0 v, t a = 25 c, i/o regulator turned off ? 1.07 1.50 ? a i sbi2c standby current with i 2 c enabled conditions are v dd = 3.3 v, t a = 25 c and cpu = 24 mhz ? 1.64 ? ? a notes 20. when v dd remains in the range from 1.71 v to 1.9 v for more than 50 s, the slew rate when moving from the 1.71 v to 1.9 v range to gre ater than 2 v must be slower than 1 v/500 s to avoid triggering por. the only other restriction on slew rates for any other voltage range or transit ion is the sr power_up parameter. 21. if powering down in standby sleep mode , to properly detect and recover from a v dd brown out condition any of the following actions must be taken: a. bring the device out of sleep before powering down. b. assure that v dd falls below 100 mv before powering back up. c. set the no buzz bit in the osc_cr0 register to k eep the voltage monitoring circuit powered during sleep. d. increase the buzz rate to assure that the falling edge of v dd is captured. the rate is configured through the pssdc bits in the slp_cfg register. for the referenced registers, refer to the technical reference manual . in deep sleep/standby sleep mode, additional low power voltage monitoring circuitry allows v dd brown out conditions to be detected and resets the device when v dd goes lower than 1.1 v at edge rates slower than 1 v/ms. 22. for proper capsense block f unctionality, if the drop in v dd exceeds 5% of the base v dd , the rate at which v dd drops should not exceed 200 mv/s. base v dd can be between 1.8 v and 5.5 v.
cy8c20x37/37s/47/47s/67/67s document number: 001-69257 rev. *f page 15 of 39 dc gpio specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 3.0 v to 5.5 v and ?40 c ? t a ? 85 c, 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, or 1.71 v to 2.4 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 10. 3.0 v to 5.5 v dc gpio specifications symbol description conditions min typ max units r pu pull-up resistor ? 4 5.60 8 k ? v oh1 high output voltage port 2 or 3 pins i oh < 10 ? a, maximum of 10 ma source current in all i/os v dd ? 0.20 ? ? v v oh2 high output voltage port 2 or 3 pins i oh = 1 ma, maximum of 20 ma source current in all i/os v dd ? 0.90 ? ? v v oh3 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 i oh < 10 ? a, maximum of 10 ma source current in all i/os v dd ? 0.20 ? ? v v oh4 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 i oh = 5 ma, maximum of 20 ma source current in all i/os v dd ? 0.90 ? ? v v oh5 high output voltage port 1 pins with ldo regulator enabled for 3 v out i oh < 10 ? a, v dd > 3.1 v, maximum of 4 i/os all sourcing 5 ma 2.85 3.00 3.30 v v oh6 high output voltage port 1 pins with ldo regulator enabled for 3 v out i oh = 5 ma, v dd > 3.1 v, maximum of 20 ma source current in all i/os 2.20 ? ? v v oh7 high output voltage port 1 pins with ldo enabled for 2.5 v out i oh < 10 ? a, v dd > 2.7 v, maximum of 20 ma source current in all i/os 2.35 2.50 2.75 v v oh8 high output voltage port 1 pins with ldo enabled for 2.5 v out i oh = 2 ma, v dd > 2.7 v, maximum of 20 ma source current in all i/os 1.90 ? ? v v oh9 high output voltage port 1 pins with ldo enabled for 1.8 v out i oh < 10 ? a, v dd > 2.7 v, maximum of 20 ma source current in all i/os 1.60 1.80 2.10 v v oh10 high output voltage port 1 pins with ldo enabled for 1.8 v out i oh = 1 ma, v dd > 2.7 v, maximum of 20 ma source current in all i/os 1.20 ? ? v v ol low output voltage i ol = 25 ma, v dd > 3.3 v, maximum of 60 ma sink current on even port pins (for example, p0[2] and p1[4]) and 60 ma sink current on odd port pins (for example, p0[3] and p1[5]) ? ? 0.75 v v il input low voltage ? ? ? 0.80 v v ih input high voltage ? 2.00 ? ? v v h input hysteresis voltage ? ? 80 ? mv i il input leakage (absolute value) ? ? 0.00 1 1 ? a c pin pin capacitance package and pin dependent te m p = 2 5 c 0.50 1.70 7 pf v illvt3.3 input low voltage with low threshold enable set, enable for port1 bit3 of io_cfg1 set to enable low threshold voltage of port1 input 0.8 v ? ? v ihlvt3.3 input high voltage with low threshold enable set, enable for port1 bit3 of io_cfg1 set to enable low threshold voltage of port1 input 1.4 ? ? v v illvt5.5 input low voltage with low threshold enable set, enable for port1 bit3 of io_cfg1 set to enable low threshold voltage of port1 input 0.8 v ? ? v ihlvt5.5 input high voltage with low threshold enable set, enable for port1 bit3 of io_cfg1 set to enable low threshold voltage of port1 input 1.7 ? ? v
cy8c20x37/37s/47/47s/67/67s document number: 001-69257 rev. *f page 16 of 39 table 11. 2.4 v to 3.0 v dc gpio specifications symbol description conditions min typ max units r pu pull-up resistor ? 4 5.60 8 k ? v oh1 high output voltage port 2 or 3 pins i oh < 10 ? a, maximum of 10 ma source current in all i/os v dd - 0.20 ? ? v v oh2 high output voltage port 2 or 3 pins i oh = 0.2 ma, maximum of 10 ma source current in all i/os v dd - 0.40 ? ? v v oh3 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 i oh < 10 ? a, maximum of 10 ma source current in all i/os v dd - 0.20 ? ? v v oh4 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 i oh = 2 ma, maximum of 10 ma source current in all i/os v dd - 0.50 ? ? v v oh5a high output voltage port 1 pins with ldo enabled for 1.8 v out i oh < 10 ? a, v dd > 2.4 v, maximum of 20 ma source current in all i/os 1.50 1.80 2.10 v v oh6a high output voltage port 1 pins with ldo enabled for 1.8 v out i oh = 1 ma, v dd > 2.4 v, maximum of 20 ma source current in all i/os 1.20 ? ? v v ol low output voltage i ol = 10 ma, maximum of 30 ma sink current on even port pins (for example, p0[2] and p1[4]) and 30 ma sink current on odd port pins (for example, p0[3] and p1[5]) ? ? 0.75 v v il input low voltage ? ? ? 0.72 v v ih input high voltage ? 1.40 ? v v h input hysteresis voltage ? ? 80 ? mv i il input leakage (absolute value) ? ? 1 1000 na c pin capacitive load on pins package and pin dependent te m p = 2 5 ? c 0.50 1.70 7 pf v illvt2.5 input low voltage with low threshold enable set, enable for port1 bit3 of io_cfg1 set to enable low threshold voltage of port1 input 0.7 v ? v ihlvt2.5 input high voltage with low threshold enable set, enable for port1 bit3 of io_cfg1 set to enable low threshold voltage of port1 input 1.2 ? v table 12. 1.71 v to 2.4 v dc gpio specifications symbol description conditions min typ max units r pu pull-up resistor ? 4 5.60 8 k ? v oh1 high output voltage port 2 or 3 pins i oh = 10 ? a, maximum of 10 ma source current in all i/os v dd ? 0.20 ? ? v v oh2 high output voltage port 2 or 3 pins i oh = 0.5 ma, maximum of 10 ma source current in all i/os v dd ? 0.50 ? ? v v oh3 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 i oh = 100 ? a, maximum of 10 ma source current in all i/os v dd ? 0.20 ? ? v v oh4 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 i oh = 2 ma, maximum of 10 ma source current in all i/os v dd ? 0.50 ? ? v
cy8c20x37/37s/47/47s/67/67s document number: 001-69257 rev. *f page 17 of 39 dc analog mux bus specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. dc low power compar ator spec ifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. v ol low output voltage i ol = 5 ma, maximum of 20 ma sink current on even port pi ns (for example, p0[2] and p1[4]) and 30 ma sink current on odd port pins (for example, p0[3] and p1[5]) ? ? 0.40 v v il input low voltage ? ? ? 0.30 v dd v v ih input high voltage ? 0.65 v dd ??v v h input hysteresis voltage ? ? 80 ? mv i il input leakage (absolute value) ? ? 1 1000 na c pin capacitive load on pins package and pin dependent temp = 25 ? c 0.50 1.70 7 pf table 12. 1.71 v to 2.4 v dc gpio specifications (continued) symbol description conditions min typ max units table 13. dc analog mux bus specifications symbol description conditions min typ max units r sw switch resistance to common analog bus ? ? ? 800 ? r gnd resistance of initialization switch to v ss ? ? ? 800 ? the maximum pin voltage for measuring r sw and r gnd is 1.8 v table 14. dc comparator specifications symbol description conditions min typ max units v lpc low power comparator (lpc) common mode maximum voltage limited to v dd 0.2 ? 1.8 v i lpc lpc supply current ? ? 10 80 ? a v oslpc lpc voltage offset ? ? 2.5 30 mv
cy8c20x37/37s/47/47s/67/67s document number: 001-69257 rev. *f page 18 of 39 comparator user module electrical sp ecifications the following table lists the guaranteed maximum and minimum spec ifications. unless stated otherwis e, the specifications are fo r the entire device voltage and temperature operating range: ?40 c ? ta ? 85 c, 1.71 v ? v dd ? 5.5 v. adc electrical specifications table 15. comparator user module electrical specifications symbol description conditions min typ max units t comp comparator response time 50 mv overdrive ? 70 100 ns offset valid from 0.2 v to 1.5 v ? 2.5 30 mv current average dc current, 50 mv overdrive ? 20 80 a psrr supply voltage > 2 v power supply rejection ratio ? 80 ? db supply voltage < 2 v power supply rejection ratio ? 40 ? db input range ? 0.2 1.5 v table 16.adc user module electrical specifications symbol description conditions min typ max units input v in input voltage range ? 0 ? vrefadc v c iin input capacitance ???5 pf r in input resistance equivalent switched cap input resistance for 8-, 9-, or 10-bit resolution 1/(500ff data clock) 1/(400ff data clock) 1/(300ff data clock) ? reference v refadc adc reference voltage ? 1.14 ? 1.26 v conversion rate f clk data clock source is chip?s internal main oscillator. see ac chip-level specifications on page 21 for accuracy 2.25 ? 6 mhz s8 8-bit sample rate data clock set to 6 mhz. sample rate = 0.001/ (2^resolution/data clock) ?23.43 ?ksps s10 10-bit sample rate da ta clock set to 6 mhz. sample rate = 0.001/ (2^resolution/data clock) ? 5.85 ? ksps dc accuracy res resolution can be set to 8, 9, or 10 bit 8 ? 10 bits dnl differential nonlinearity ? ?1 ? +2 lsb inl integral nonlinearity ? ?2 ? +2 lsb e offset offset error 8-bit resolution 0 3.20 19.20 lsb 10-bit resolution 0 12.80 76.80 lsb e gain gain error for any resolution ?5 ? +5 %fsr power i adc operating current ? ? 2.10 2.60 ma psrr power supply rejection ratio psrr (v dd > 3.0 v) ? 24 ? db psrr (v dd < 3.0 v) ? 30 ? db
cy8c20x37/37s/47/47s/67/67s document number: 001-69257 rev. *f page 19 of 39 dc por and lvd specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. dc programming specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 17. dc por and lvd specifications symbol description conditions min typ max units v por0 1.66 v selected in psoc designer v dd must be greater than or equal to 1.71 v during startup, reset from the xres pin, or reset from watchdog. 1.61 1.66 1.71 v v por1 2.36 v selected in psoc designer ? 2.36 2.41 v por2 2.60 v selected in psoc designer ? 2.60 2.66 v por3 2.82 v selected in psoc designer ? 2.82 2.95 v lvd0 2.45 v selected in psoc designer ? 2.40 2.45 2.51 v v lvd1 2.71 v selected in psoc designer 2.64 [23] 2.71 2.78 v lvd2 2.92 v selected in psoc designer 2.85 [24] 2.92 2.99 v lvd3 3.02 v selected in psoc designer 2.95 [25] 3.02 3.09 v lvd4 3.13 v selected in psoc designer 3.06 3.13 3.20 v lvd5 1.90 v selected in psoc designer 1.84 1.90 2.32 v lvd6 1.80 v selected in psoc designer 1.75 [26] 1.80 1.84 v lvd7 4.73 v selected in psoc designer 4.62 4.73 4.83 table 18. dc programming specifications symbol description conditions min typ max units v ddiwrite supply voltage for flash write operations ? 1.71 ? 5.25 v i ddp supply current during programming or verify ? ? 5 25 ma v ilp input low voltage during programming or verify see appropriate dc gpio specifications on page 15 ? ? v il v v ihp input high voltage during programming or verify see appropriate dc gpio specifications on page 15 v ih ? ? v i ilp input current when applying v ilp to p1[0] or p1[1] during programming or verify driving internal pull-down resistor ? ? 0.2 ma i ihp input current when applying v ihp to p1[0] or p1[1] during programming or verify driving internal pull-down resistor ? ? 1.5 ma v olp output low voltage during programming or verify ? ? v ss + 0.75 v v ohp output high voltage during programming or verify see appropriate dc gpio specifications on page 15 . for v dd > 3v use v oh4 in table 10 on page 15 . v oh ? v dd v flash enpb flash write endurance erase/write cycles per block 50,000 ? ? ? flash dr flash data retention following maximum flash write cycles; ambient temperature of 55 c 20 ? ? years notes 23. always greater than 50 mv above v ppor1 voltage for falling supply. 24. always greater than 50 mv above v ppor2 voltage for falling supply. 25. always greater than 50 mv above v ppor3 voltage for falling supply. 26. always greater than 50 mv above v ppor0 voltage for falling supply.
cy8c20x37/37s/47/47s/67/67s document number: 001-69257 rev. *f page 20 of 39 dc i 2 c specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 3.0 v to 5.5 v and ?40 c ? t a ? 85 c, 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, or 1.71 v to 2.4 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. shield driver dc specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 3.0 v to 5.5 v and ?40 c ? t a ? 85 c, 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, or 1.71 v to 2.4 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. dc idac specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 19. dc i 2 c specifications [27] symbol description conditions min typ max units v ili2c input low level 3.1 v v dd 5.5 v ? ? 0.25 v dd v 2.5 v v dd 3.0 v ? ? 0.3 v dd v 1.71 v v dd 2.4 v ? ? 0.3 v dd v v ihi2c input high level 1.71 v v dd 5.5 v 0.65 v dd ??v table 20. shield driver dc specifications symbol description conditions min typ max units v ref reference buffer output 1.7 v v dd 5.5 v 0.942 ? 1.106 v v refhi reference buffer output 1.7 v v dd 5.5 v 1.104 ? 1.296 v table 21. dc idac specifications (8-bit idac) symbol description min typ max units notes idac_dnl differential nonlinearity ?1 ? 1 lsb idac_dnl integral nonlinearity ?2 ? 2 lsb idac_current range = 4x 138 ? 169 a dac setting = 127 dec range = 8x 138 ? 169 a dac setting = 64 dec table 22. dc idac specifications (7-bit idac) symbol description min typ max units notes idac_dnl differential nonlinearity ?1 ? 1 lsb idac_dnl integral nonlinearity ?2 ? 2 lsb idac_current range = 4x 137 ? 168 a dac setting = 127 dec range = 8x 138 ? 169 a dac setting = 64 dec note 27. pull-up resistors on i2c interface cannot be connected to a supply voltage that is more than 0.7 v higher than the cy8c20xx7/ s/h/l power supply. see the cy8c20xx7 silicon errata document for more details.
cy8c20x37/37s/47/47s/67/67s document number: 001-69257 rev. *f page 21 of 39 ac chip-level specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 23. ac chip-level specifications symbol description conditions min typ max units f imo24 imo frequency at 24 mhz setting ? 22.8 24 25.2 mhz f imo12 imo frequency at 12 mhz setting ? 11.4 12 12.6 mhz f imo6 imo frequency at 6 mhz setting ? 5.7 6.0 6.3 mhz f cpu cpu frequency ? 0.75 ? 25.20 mhz f 32k1 ilo frequency ? 15 32 50 khz f 32k_u ilo untrimmed frequency ? 13 32 82 khz dc imo duty cycle of imo ? 40 50 60 % dc ilo ilo duty cycle ? 40 50 60 % sr power_up power supply slew rate v dd slew rate during power-up ? ? 250 v/ms t xrst external reset pulse width at power-up after supply voltage is valid 1 ? ? ms t xrst2 external reset pulse width after power-up [28] applies after part has booted 10 ? ? ? s t jit_imo [29] 6 mhz imo cycle-to-cycle jitter (rms) ? ? 0.7 6.7 ns 6 mhz imo long term n cycle-to-cycle jitter (rms); n = 32 ? ? 4.3 29.3 ns 6 mhz imo period jitter (rms) ? ? 0.7 3.3 ns 12 mhz imo cycle-to-cycle jitter (rms) ? ? 0.5 5.2 ns 12 mhz imo long term n cycle-to-cycle jitter (rms); n = 32 ???2.35.6ns 12 mhz imo period jitter (rms) ? ? 0.4 2.6 ns 24 mhz imo cycle-to-cycle jitter (rms) ? ? 1.0 8.7 ns 24 mhz imo long term n cycle-to-cycle jitter (rms); n = 32 ? ? 1.4 6.0 ns 24 mhz imo period jitter (rms) ? ? 0.6 4.0 ns note 28. the minimum required xres pulse length is longer when programming the device (see table 27 on page 23 ). 29. see the cypress jitter sp ecifications application note, understanding datasheet jitter specific ations for cypress timing products ? an5054 for more information.
cy8c20x37/37s/47/47s/67/67s document number: 001-69257 rev. *f page 22 of 39 ac general purpose i/o specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. figure 9. gpio timing diagram ac comparator specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. ac external clock specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 24. ac gpio specifications symbol description conditions min typ max units f gpio gpio operating frequency normal strong mode port 0, 1 0 0 ? ? 6 mhz for 1.71 v cy8c20x37/37s/47/47s/67/67s document number: 001-69257 rev. *f page 23 of 39 ac programming specifications figure 10. ac waveform the following table lists the guaranteed maximum and minimum s pecifications for the entire vo ltage and temperature ranges. table 27. ac programming specifications symbol description conditions min typ max units t rsclk rise time of sclk ? 1 ? 20 ns t fsclk fall time of sclk ? 1 ? 20 ns t ssclk data setup time to falling edge of sclk ? 40 ? ? ns t hsclk data hold time from falling edge of sclk ? 40 ? ? ns f sclk frequency of sclk ? 0 ? 8 mhz t eraseb flash erase time (block) ? ? ? 18 ms t write flash block write time ? ? ? 25 ms t dsclk data out delay from falling edge of sclk 3.6 ? v dd ? ? 60 ns t dsclk3 data out delay from falling edge of sclk 3.0 ? v dd ? 3.6 ? ? 85 ns t dsclk2 data out delay from falling edge of sclk 1.71 ? v dd ? 3.0 ? ? 130 ns t xrst3 external reset pulse width after power-up required to enter programming mode when coming out of sleep 300 ? ? ? s t xres xres pulse length ? 300 ? ? ? s t vddwait [30] v dd stable to wait-and-poll hold off ? 0.1 ? 1 ms t vddxres [30] v dd stable to xres assertion delay ? 14.27 ? ? ms t poll sdat high pulse time ? 0.01 ? 200 ms t acq [30] ?key window? time after a v dd ramp acquire event, based on 256 ilo clocks. ? 3.20 ? 19.60 ms t xresini [30] ?key window? time after an xres event, based on 8 ilo clocks ? 98 ? 615 ? s sclk (p1[1]) t rsclk t fsclk sdata (p1[0]) t ssclk t hsclk t dsclk note 30. valid from 5 to 50 c. see the spec, cy8c20x66, cy8c20x46, cy8c20x36, cy7c643xx, cy7c604xx, cy8ctst2xx, cy8ctmg2xx, cy8c20x67, cy8c20x47, cy8c20x37, programming spec for more details.
cy8c20x37/37s/47/47s/67/67s document number: 001-69257 rev. *f page 24 of 39 ac i 2 c specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. figure 11. definition for timing for fast/standard mode on the i 2 c bus table 28. ac characteristics of the i 2 c sda and scl pins symbol description standard mode fast mode units min max min max f scl scl clock frequency 0 100 0 400 khz t hd;sta hold time (repeated) start condition. afte r this period, the first clock pulse is generated 4.0 ?0.6 ?s t low low period of the scl clock 4.7 ?1.3 ?s t high high period of the scl clock 4.0 ?0.6 ?s t su;sta setup time for a repeated start condition 4.7 ?0.6 ?s t hd;dat [31] data hold time 20 3.45 20 0.90 s t su;dat data setup time 250 ? 100 [32] ?ns t su;sto setup time for stop condition 4.0 ?0.6 ?s t buf bus free time between a stop and start condition 4.7 ?1.3 ?s t sp pulse width of spikes are suppressed by the input filter ? ?050ns notes 31. to wake up from sleep using i2c hardware addr ess match event, i2c interface needs 20 ns hold time on sda line with respect to falling edge of scl. see the cy8c20xx7 silicon errata document for more details. 32. a fast-mode i 2 c-bus device can be used in a standard mode i 2 c-bus system, but the requirement t su;dat ? 250 ns must then be met. this automatically be the case if the device does not stre tch the low period of the scl signal. if such devi ce does stretch the low period of the scl sig nal, it must output the next data bit to the sda line t rmax + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released.
cy8c20x37/37s/47/47s/67/67s document number: 001-69257 rev. *f page 25 of 39 figure 12. spi master mode 0 and 2 figure 13. spi master mode 1 and 3 table 29. spi master ac specifications symbol description conditions min typ max units f sclk sclk clock frequency v dd ? ? 2.4 v v dd < 2.4 v ? ? ? ? 6 3 mhz mhz dc sclk duty cycle ? ? 50 ? % t setup miso to sclk setup time v dd ? 2.4 v v dd < 2.4 v 60 100 ? ? ? ? ns ns t hold sclk to miso hold time ? 40 ? ? ns t out_val sclk to mosi valid time ? ? ? 40 ns t out_h mosi high time ? 40 ? ? ns 1/f sclk t low t high t out_h t hold t setup t out_su msb lsb spi master, modes 0 and 2 sclk (mode 0) sclk (mode 2) miso (input) mosi (output) 1/f sclk t high t low t out_h t hold t setup sclk (mode 1) sclk (mode 3) miso (input) mosi (output) spi master, modes 1 and 3 t out_su msb msb lsb lsb
cy8c20x37/37s/47/47s/67/67s document number: 001-69257 rev. *f page 26 of 39 figure 14. spi slave mode 0 and 2 figure 15. spi slave mode 1 and 3 table 30. spi slave ac specifications symbol description conditions min typ max units f sclk sclk clock frequency ? ? ? 4 mhz t low sclk low time ? 42 ? ? ns t high sclk high time ? 42 ? ? ns t setup mosi to sclk setup time ? 30 ? ? ns t hold sclk to mosi hold time ? 50 ? ? ns t ss_miso ss high to miso valid ? ? ? 153 ns t sclk_miso sclk to miso valid ? ? ? 125 ns t ss_high ss high time ? 50 ? ? ns t ss_clk time from ss low to first sclk ? 2/sclk ? ? ns t clk_ss time from last sclk to ss high ? 2/sclk ? ? ns t clk_ss t ss_high 1/f sclk t low t high t out_h t hold t setup t ss_miso t ss_clk msb lsb spi slave, modes 0 and 2 /ss sclk (mode 0) sclk (mode 2) miso (output) mosi (input) t clk_ss 1/f sclk t high t low t sclk_miso t out_h t hold t setup t ss_clk /ss sclk (mode 1) sclk (mode 3) miso (output) mosi (input) spi slave, modes 1 and 3 t ss_miso msb msb lsb lsb
cy8c20x37/37s/47/47s/67/67s document number: 001-69257 rev. *f page 27 of 39 packaging information this section illustrates the packaging specifications for the cy8c20x37/47/67 psoc device, along with the thermal impedances fo r each package. important note emulation tools may require a larger area on the target pcb than the chip?s f ootprint. for a detailed description of the emulation tools? dimensions, refer to the document titled psoc emulator pod dimensions at http://www.cypress.com/design/mr10161 . figure 16. 16-pin (150 mil) soic figure 17. 16-pin qfn no center pad (3 x 3 x 0.6 mm) package outline (sawn) 51-85068 *d 001-09116 *f
cy8c20x37/37s/47/47s/67/67s document number: 001-69257 rev. *f page 28 of 39 figure 18. 24-pin (4 4 0.6 mm) qfn figure 19. 32-pin (5 5 0.6 mm) qfn 001-13937 *d 001-42168 *d
cy8c20x37/37s/47/47s/67/67s document number: 001-69257 rev. *f page 29 of 39 figure 20. 48-pin (6 6 0.6 mm) qfn important notes for information on the preferred dimensions for mountin g qfn packages, see the following application note at http://www.amkor.com/products/n otes_papers/mlfappnote.pdf . pinned vias for thermal conduction are not required for the low power psoc device. 001-57280 *c
cy8c20x37/37s/47/47s/67/67s document number: 001-69257 rev. *f page 30 of 39 thermal impedances capacitance on crystal pins solder reflow peak temperature table 33 shows the solder reflow temperature limits that must not be exceeded. table 31. thermal impedances per package package typical ? ja [33] 16-pin soic 95 ? c/w 16-pin qfn 33 ? c/w 24-pin qfn [34] 21 ? c/w 32-pin qfn [34] 20 ? c/w 48-pin qfn [34] 18 ? c/w 30-ball wlcsp 54 ? c/w table 32. typical package capacitance on crystal pins package package capacitance 32-pin qfn 3.2 pf 48-pin qfn 3.3 pf table 33. solder reflow peak temperature package maximum peak temperature (t c ) maximum time above t c ? 5 ? c 16-pin soic 260 ? c 30 seconds 16-pin qfn 260 ? c 30 seconds 24-pin qfn 260 ? c 30 seconds 32-pin qfn 260 ? c 30 seconds 48-pin qfn 260 ? c 30 seconds 30-ball wlcsp 260 ? c 30 seconds notes 33. t j = t a + power ? ja . 34. to achieve the thermal impedance specifie d for the qfn package, the center thermal pad must be so ldered to the pcb ground pl ane.
cy8c20x37/37s/47/47s/67/67s document number: 001-69257 rev. *f page 31 of 39 development tool selection software psoc designer? at the core of the psoc development software suite is psoc designer, used to generate psoc firmware applications. psoc designer is a microsoft ? windows-based, integrated development environment for the programmable system-on- chip (psoc) devices. the psoc designer ide and application runs on windows xp and windows vista. this system provides design database management by project, in-system programming support, and built-in support for third- party assemblers and c comp ilers. psoc designer also supports c language compilers developed specifically for the devices in the psoc family. psoc designer is available free of charge at http://www.cypress. com/psocdesigner and includes a free c compiler. psoc designer soft ware subsystems you choose a base device to work with and then select different onboard analog and digital components called user modules that use the psoc blocks. examples of user modules are adcs, dacs, amplifiers, and filters. you configure the user modules for your chosen application and connect them to each other and to the proper pins. then you generate your project. this prepopulates your project with apis and libraries that you can use to program your application. the tool also supports easy development of multiple configurations and dynamic reconfiguration. dynamic reconfiguration allows for changi ng configurations at run time. code generation tools psoc designer supports multiple third- party c compilers and assemblers. the code generation tools work seamlessly within the psoc designer interface and have been tested with a full range of debugging tools. the choice is yours. assemblers. the assemblers allow assembly code to be merged seamlessly with c code. link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. c language compilers. c language compilers are available that support the psoc family of devices. the products allow you to create complete c programs fo r the psoc family devices. the optimizing c compilers provide all the features of c tailored to the psoc architecture. they come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. psoc programmer psoc programmer is flexible enough and is used on the bench in development and is also suitable for factory programming. psoc programmer works either as a standalone programming application or operates directly from psoc designer. psoc programmer software is compatible with both psoc ice cube in-circuit emulator and psoc miniprog. psoc programmer is available free of cost at http://www.cypress. com/psocprogrammer . development kits all development kits are sold at the cypress online store . evaluation tools all evaluation tools are sold at the cypress online store . cy3210-miniprog1 the cy3210-miniprog1 kit allows you to program psoc devices through the miniprog1 programming unit. the miniprog is a small, compact prototyping programmer that connects to the pc through a provided usb 2.0 cable. the kit includes: miniprog programming unit minieval socket programming and evaluation board 28-pin cy8c29466-24pxi pdip psoc device sample 28-pin cy8c27443-24pxi pdip psoc device sample psoc designer software cd getting started guide usb 2.0 cable cy3210-psoceval1 the cy3210-psoceval1 kit features an evaluation board and the miniprog1 programming unit. the evaluation board includes an lcd module, potentiometer, leds, and plenty of bread- boarding space to meet all of your evaluation needs. the kit includes: evaluation board with lcd module miniprog programming unit two 28-pin cy8c29466-24pxi pdip psoc device samples psoc designer software cd getting started guide usb 2.0 cable device programmers all device programmers are purchased from the cypress online store . cy3216 modular programmer the cy3216 modular programmer kit features a modular programmer and the miniprog1 programming unit. the modular programmer includes three programming module cards and supports multiple cypress products. the kit includes: modular programmer base three programming module cards miniprog programming unit psoc designer software cd getting started guide usb 2.0 cable
cy8c20x37/37s/47/47s/67/67s document number: 001-69257 rev. *f page 32 of 39 cy3207issp in-system serial programmer (issp) the cy3207issp is a production programmer. it includes protection circuitry and an industrial case that is more robust than the miniprog in a production-programming environment. note cy3207issp needs special software and is not compatible with psoc programmer. the kit includes: cy3207 programmer unit psoc issp software cd 110 ~ 240 v power supply, euro-plug adapter usb 2.0 cable accessories (emulation and programming) third party tools several tools have been specially designed by the following thir d-party vendors to accompany psoc devices during development an d production. specific details for each of these tools can be found at http://www.cypress.com under documentation > evaluation boards. build a psoc emulator into your board for details on how to emulate your circuit before going to volume production using an on-chip debug (ocd) non-production psoc device, see the application note debugging - build a psoc emulator into your board ? an2323. table 34. emulation and programming accessories part number pin package flex-pod kit [35] foot kit [36] adapter [37] cy8c20237-24lkxi 16 qfn cy3250-20246qfn cy3250-20246qfn-pod see note 34 cy8c20247-24lkxi 16 qfn cy3250-20246qfn cy3250-20246qfn-pod see note 37 cy8c20337-24lqxi 24 qfn cy3250-20346 qfn cy3250-20346qfn-pod see note 34 cy8c20347-24lqxi 24 qfn cy3250-20346 qfn cy3250-20346qfn-pod see note 37 cy8c20437-24lqxi 32 qfn cy3250-20466 qfn cy3250-20466qfn-pod see note 34 cy8c20447-24lqxi 32 qfn cy3250-20466 qfn cy3250-20466qfn-pod see note 37 cy8c20467-24lqxi 32 qfn cy3250-20466 qfn cy3250-20466qfn-pod see note 37 cy8c20637-24lqxi 48 qfn cy3250-20666 qfn cy3250-20666qfn-pod see note 37 cy8c20647-24lqxi 48 qfn cy3250-20666 qfn cy3250-20666qfn-pod see note 37 cy8c20667-24lqxi 48 qfn cy3250-20666 qfn cy3250-20666qfn-pod see note 37 notes 35. flex-pod kit includes a practice flex-pod and a practice pcb, in a ddition to two flex-pods. 36. foot kit includes surface mount feet that can be soldered to the target pcb. 37. programming adapter converts non-dip package to dip footprint. specific details and ordering information for each of the ada pters can be found at http://www.emulation.com .
cy8c20x37/37s/47/47s/67/67s document number: 001-69257 rev. *f page 33 of 39 ordering information the following table lists the cy8c20x37/47/67/s psoc devices' key package features and ordering codes. note 38. dual-function digital i/o pins also connect to the common analog mux . table 35. psoc device key features and ordering information ordering code package flash (bytes) sram (bytes) capsense sensors digital i/o pins analog inputs [38] xres pin adc cy8c20237-24sxi 16-pin soic 8 k 1 k 12 13 13 yes yes cy8c20247-24sxi 16-pin soic 16 k 2 k 12 13 13 yes yes cy8c20247s-24sxi 16-pin soic 16 k 2 k 12 13 13 yes yes cy8c20237-24lkxi 16-pin qfn 8 k 1 k 12 13 13 yes yes cy8c20237-24lkxit 16-pin qfn (tape and reel) 8 k 1 k 12 13 13 yes yes cy8c20247-24lkxi 16-pin qfn 16 k 2 k 12 13 13 yes yes cy8c20247-24lkxit 16-pin qfn (tape and reel) 16 k 2 k 12 13 13 yes yes cy8c20247s-24lkxi 16-pin qfn 16 k 2 k 12 13 13 yes yes cy8c20247s-24lkxit 16-pin qfn (tape and reel) 16 k 2 k 12 13 13 yes yes cy8c20337-24lqxi 24-pin qfn 8 k 1 k 18 19 19 yes yes cy8c20337-24lqxit 24-pin qfn (tape and reel) 8 k 1 k 18 19 19 yes yes cy8c20347-24lqxi 24-pin qfn 16 k 2 k 18 19 19 yes yes cy8c20347-24lqxit 24-pin qfn (tape and reel) 16 k 2 k 18 19 19 yes yes cy8c20347s-24lqxi 24-pin qfn 16 k 2 k 18 19 19 yes yes cy8c20347s-24lqxit 24-pin qfn (tape and reel) 16 k 2 k 18 19 19 yes yes cy8c20437-24lqxi 32-pin qfn 8 k 1 k 27 28 28 yes yes cy8c20437-24lqxit 32-pin qfn (tape and reel) 8 k 1 k 27 28 28 yes yes cy8c20447-24lqxi 32-pin qfn 16 k 2 k 27 28 28 yes yes cy8c20447-24lqxit 32-pin qfn (tape and reel) 16 k 2 k 27 28 28 yes yes cy8c20447s-24lqxi 32-pin qfn 16 k 2 k 27 28 28 yes yes cy8c20447s-24lqxit 32-pin qfn (tape and reel) 16 k 2 k 27 28 28 yes yes cy8c20467-24lqxi 32-pin qfn 32 k 2 k 27 28 28 yes yes cy8c20467-24lqxit 32-pin qfn (tape and reel) 32 k 2 k 27 28 28 yes yes cy8c20467s-24lqxi 32-pin qfn 32 k 2 k 27 28 28 yes yes cy8c20467s-24lqxit 32-pin qfn (tape and reel) 32 k 2 k 27 28 28 yes yes cy8c20637-24lqxi 48-pin qfn 8 k 1 k 31 32 32 yes yes cy8c20637-24lqxit 48-pin qfn (tape and reel) 8 k 1 k 31 32 32 yes yes cy8c20647-24lqxi 48-pin qfn 16 k 2 k 31 32 32 yes yes cy8c20647-24lqxit 48-pin qfn (tape and reel) 16 k 2 k 31 32 32 yes yes cy8c20647s-24lqxi 48-pin qfn 16 k 2 k 31 32 32 yes yes cy8c20647s-24lqxit 48-pin qfn (tape and reel) 16 k 2 k 31 32 32 yes yes cy8c20667-24lqxi 48-pin qfn 32 k 2 k 31 32 32 yes yes cy8c20667-24lqxit 48-pin qfn (tape and reel) 32 k 2 k 31 32 32 yes yes
cy8c20x37/37s/47/47s/67/67s document number: 001-69257 rev. *f page 34 of 39 ordering code definitions cy8c20667s-24lqxi 48-pin qfn 32 k 2 k 31 32 32 yes yes cy8c20667s-24lqxit 48-pin qfn (tape and reel) 32 k 2 k 31 32 32 yes yes cy8c20747-24fdxc 30-pin wlcsp 16 k 1 k 26 27 27 yes yes cy8c20747-24fdxct 30-pin wlcsp (tape and reel) 16 k 1 k 26 27 27 yes yes cy8c20767-24fdxc 30-pin wlcsp 32 k 2 k 26 27 27 yes yes cy8c20767-24fdxct 30-pin wlcsp (tape and reel) 32 k 2 k 26 27 27 yes yes table 35. psoc device key features and ordering information (continued) ordering code package flash (bytes) sram (bytes) capsense sensors digital i/o pins analog inputs [38] xres pin adc cy marketing code: 8 = psoc 8 c 20 technology code: c = cmos company id: cy = cypress xx7 family code part number x s = smartsense? auto-tuning enabled 24 speed grade = 24 mhz xx package types : xx = s, lk, lq, or fd s = 16-pin soic lk = 16-pin qfn (no center pad) lq = 24-pin qfn, 32-pin qfn, 48-pin qfn fd = 30-ball wlcsp (t) - x x pb-free temperature range: x = c or i c = commercial; i = industrial tape and reel
cy8c20x37/37s/47/47s/67/67s document number: 001-69257 rev. *f page 35 of 39 acronyms the following table lists the acronyms that are used in this document. reference documents technical reference manual for cy20xx7 devices in-system serial programmi ng (issp) protocol for 20xx7 host sourced serial programming for 20xx7 devices document conventions units of measure ta b l e 3 7 lists all the abbreviation s used to measure the psoc devices. table 36. acronyms used in this document acronym description ac alternating current adc analog-to-digital converter api application programming interface cmos complementary metal oxide semiconductor cpu central processing unit dac digital-to-analog converter dc direct current esd electrostatic discharge fsr full scale range gpio general purpose input/output i 2 c inter-integrated circuit ice in-circuit emulator ilo internal low speed oscillator imo internal main oscillator i/o input/output issp in-system serial programming lcd liquid crystal display ldo low dropout (regulator) led light-emitting diode lpc low power comparator lsb least-significant bit lvd low voltage detect mcu micro-controller unit mips million instructions per second miso master in slave out mosi master out slave in msb most-significant bit ocd on-chip debug pcb printed circuit board por power on reset psrr power supply rejection ratio pwrsys power system psoc programmable system-on-chip qfn quad flat no-lead sclk serial i 2 c clock sda serial i 2 c data sdata serial issp data soic small outline integrated circuit spi serial peripheral interface sram static random access memory ss slave select usb universal serial bus wlcsp wafer level chip scale package table 37. units of measure symbol unit of measure c degree celsius db decibel khz kilohertz ksps kilo samples per second k ? kilohm mhz megahertz ? a microampere ? s microsecond ma milliampere mm millimeter ms millisecond mv millivolt na nanoampere ns nanosecond ? ohm % percent pf picofarad v volt w watt
cy8c20x37/37s/47/47s/67/67s document number: 001-69257 rev. *f page 36 of 39 numeric naming hexadecimal numbers are represented with all letters in uppercas e with an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? pr efix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, 01010100b? or ?01000011b?). numbers not indicated by an ?h?, ?b?, or 0x are decimal. glossary crosspoint connection connection between any gpio combination via analog multiplexer bus. differential non linearity ideally, any two adjacent digital co des correspond to output analog voltages that are exactly one lsb apart. differential non-linearity is a measure of the worst case deviation from the ideal 1 lsb step. hold time hold time is the time following a clock event during which the data input to a latch or flip- flop must remain stable in order to guarantee that the latched data is correct. i 2 c it is a serial multi-master bus used to connect low speed peripherals to mcu. integral nonlinearity it is a term describing the maximum deviation between the idea l output of a dac/adc and the actual output level. latch-up current current at which the latch-up test is conducted according to jesd78 standard (at 125 degree celsius) power supply rejection ratio (psrr) the psrr is defined as th e ratio of the change in supply voltage to the corresponding change in output voltage of the device. scan the conversion of all sensor capacitances to digital values. setup time period r equired to prepare a device, machine, proc ess, or system for it to be ready to function. signal-to-noise ratio the ratio between a capacitive finger signal and system noise. spi serial peripheral interface is a synchronous serial data link standard.
cy8c20x37/37s/47/47s/67/67s document number: 001-69257 rev. *f page 37 of 39 document history page document title: cy8c20x37/37s/47/47s/67/67s, 1.8 v capsense ? controller with sm artsense? auto-tuning 31 buttons, 6 sliders document number: 001-69257 revision ecn orig. of change submission date description of change ** 3276782 dst 06/27/2011 new silicon and document *a 3327230 dst 07/28/2011 changed 48-pin dimensions to 6 6 0.6 mm qfn updated pins name in table 3 on page 9 and removed usb column and updated dimensions for 48-pin parts in table 35 on page 33 updated figure 20 on page 29 removed ice and debugger sections. removed cy3215 development kit and cy3280-20x66 ucc sections. updated ordering information . *b 3403111 yva 10/12/2011 moved status from advance to preliminary. updated ordering information removed the row named ?48- pin (6 6 mm) qfn (ocd)?. changed all 48-pin ordering code column from cy8c20xxx-24ltxx to cy8c20xxx-24lqxx. updated 16-pin soic and 16-pin qfn package drawings. *c 3473317 dst 12/23/2011 updated features . updated pinouts (removed psoc in captions of figure 2 , figure 3 , figure 4 , figure 6 , and figure 7 ). updated dc chip-level specifications under electrical specifications (updated typical value of i dd24 parameter from 3.32 ma to 2.88 ma, updated typical value of i dd12 parameter from 1.86 ma to 1.71 ma, updated typical value of i dd6 parameter from 1.13 ma to 1. 16 ma, updated maximum value of i sb0 parameter from 0.50 a to 1.1 a, added i sbi2c parameter and its details). updated dc gpio specifications under electrical specifications (added the parameters namely v illvt3.3, v ihlvt3.3, v illvt5.5, v ihlvt5.5 and their details in ta b l e 1 0 , added the parameters namely v illvt2.5 , v ihlvt2.5 and their details in ta b l e 11 ). added the following sections namely dc i2c specifications , shield driver dc specifications , and dc idac specifications under electrical specifications . updated ac chip-level specifications (added the parameter namely t jit_imo and its details). updated ordering information (updated ta b l e 3 5 ). *d 3510277 yva/dst 02/16/2012 added cy8c20x37/37s/47/4 7s/67/67s part numbers and changed title to ?1.8 v capsense? controller with smartsense? auto-tuning 31 buttons, 6 sliders? updated features . modified comparator blocks in logic block diagram . replaced smartsense with smartsense auto-tuning. added cy8c20xx7s part numbers in pin definitions. added footnote for ta b l e 1 9 . updated table 20 and ta b l e 2 1 and added table 22 . updated f 32k1 min value. updated data hold time min values. updated cy8c206x7 part information in ta b l e 3 4 . updated ordering information . *e 3539259 dst 03/01/2012 changed datasheet status from preliminary to final. updated all pinouts to include driven shield output (optional) information. updated min value for v lpc ta b l e 1 4 . updated offset and input range in table 15 .
cy8c20x37/37s/47/47s/67/67s document number: 001-69257 rev. *f page 38 of 39 *f 3645807 dst/bvi 07/03/2012 updated f sclk parameter in the table 30, ?spi slave ac specifications,? on page 26 changed t out_high to t out_h in table 29, ?spi master ac specifications,? on page 25 updated features section, ?progra mmable pin configurations? bullet: included the following sub-bullet point - 5 ma source current on port 0 and 1 and 1 ma on port 2,3 and 4 changed the bullet point ?high sink current of 25 ma for each gpio? to ?high sink current of 25 ma for each gpi o. total 120 ma maximum sink current per chip? added ?quietzone? controller? bullet and updated ?low power capsense ? block with smartsense? auto-tuning? bullet. updated package diagrams 001-13937 to *d and 001-57280 to *c revisions. document history page document title: cy8c20x37/37s/47/47s/67/67s, 1.8 v capsense ? controller with sm artsense? auto-tuning 31 buttons, 6 sliders document number: 001-69257
document number: 001-69257 rev. *f revised july 3, 2012 page 39 of 39 all products and company names mentioned in this document may be the trademarks of their respective holders. cy8c20x37/37s/47/47s/67/67s ? cypress semiconductor corporation, 2011-2012. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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